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mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 description the mh16s72ama is 16777216 - word by 72-bit synchronous dram module. this consists of eighteen industry standard 16mx4 synchronous drams in tsop and one industory standard eeprom in tssop. the mounting of tsop on a card edge dual inline package provides any application where high densities and large quantities of memory are required. this is a socket type - memory modules, suitable for easy interchange or addition of modules. features clock frequency 125mhz/100mhz/83mhz single 3.3v?.3v power supply fully synchronous operation referenced to clock rising edge burst length- 1/2/4/8(programmable) dual bank operation controlled by ba0,1(bank address) frequency -12 83mhz /cas latency- 2/3(programmable) application main memory or graphic memory in computer systems auto precharge / all bank precharge controlled by a10 burst type- sequential / interleave(programmable) column access - random lvttl interface auto refresh and self refresh 4096 refresh cycle /64ms clk access time 8ns(cl=3) -8 125mhz 6ns(cl=3) -10 100mhz 8ns(cl=3) 1pin 10pin 11pin 40pin 41pin 84pin front side 85pin 94pin 95pin 124pin 125pin 168pin back side 1 utilizes industry standard 16m x 4 synchronous drams tsop and industry standard eeprom in tssop 168-pin (84-pin dual in-line package) (component sdram)
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 vss 43 vss 85 vss 127 vss 2 dq0 44 nc 86 dq32 128 cke0 3 dq1 45 /s2 87 dq33 129 nc 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6 vdd 48 nc 90 vdd 132 nc 7 dq4 49 vdd 91 dq36 133 vdd 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 vdd 101 dq45 143 vdd 18 vdd 60 dq20 102 vdd 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 nc 105 cb4 147 nc 22 cb1 64 vss 106 cb5 148 vss 23 vss 65 dq21 107 vss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 vdd 68 vss 110 vdd 152 vss 27 /we0 69 dq24 111 /cas 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 /s0 72 dq27 114 nc 156 dq59 31 nc 73 vdd 115 /ras 157 vdd 32 vss 74 dq28 116 vss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 vss 120 a7 162 vss 37 a8 79 ck2 121 a9 163 ck3 38 a10 80 nc 122 ba0 164 nc 39 ba1 81 nc 123 a11 165 sa0 40 vdd 82 sda 124 vdd 166 sa1 41 vdd 83 scl 125 ck1 167 sa2 42 ck0 84 vdd 126 nc 168 vdd nc = no connection 2
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 block diagram 3 ck0 serial pd scl sda sa0 sa1 sa2 a0 a1 a2 vcc vss d0 - d17 d0 - d17 /s0 /s2 dqmb0 dqmb4 dqmb1 dqmb5 dqmb2 dqmb6 dqmb3 dqmb7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 cke0 d0 - d8 /ras d0 - d17 /cas d0 - d17 /we d0 - d17 ba0,ba1,a<11:0> d0 - d17 ck1 ck,dq=10 w 5sdrams 5sdrams ck2 ck3 4sdrams 4sdrams i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d0 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d0 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d0 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d0 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d9 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d10 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d11 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d12 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d5 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d6 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d7 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d8 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d14 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d15 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d16 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d17 cke1 d9 - d17 3.3v i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d0 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d1 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d2 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d3 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d13 i/o 0 i/o 1 i/o 2 i/o 3 dqm /cs d4
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 serial presence detect table i byte function described spd enrty data spd data(hex) 0 defines # bytes written into serial memory at module mfgr 128 80 1 total # bytes of spd memory device 256 bytes 08 2 fundamental memory type sdram 04 3 # row addresses on this assembly a0-a11 0c 4 # column addresses on this assembly a0-a9 0a 5 # module banks on this assembly 1bank 01 6 data width of this assembly... x72 48 7 ... data width continuation 0 00 8 voltage interface standard of this assembly lvttl 01 9 sdram cycletime at max. supported cas latency (cl). -8 8ns 80 cycle time for cl=3 -10 10ns a0 -12 12ns c0 10 sdram access from clock -8 6ns 60 tac for cl=3 -10 8ns 80 -12 8ns 80 11 dimm configuration type (non-parity,parity,ecc) ecc 02 12 refresh rate/type self refresh(15.625us) 80 13 sdram width,primary dram x4 04 14 error checking sdram data width x4 04 15 minimum clock delay,back to back random column addresses 1 01 16 burst lengths supported 1/2/4/8 0f 17 # banks on each sdram device 4bank 04 18 cas# latency cl=2/3 06 19 cs# latency 0 01 20 write latency 0 01 21 sdram module attributes non-buffered,non-registered 00 22 sdram device attributes:general precharge all,auto precharge 06 23 sdram cycle time(2nd highest cas latency) -8 13ns d0 cycle time for cl=2 -10 14ns e0 -12 15ns f0 24 sdram access form clock(2nd highest cas latency) -8 7ns 70 tac for cl=2 -10 8ns 80 -12 9ns 90 25 sdram cycle time(3rd highest cas latency) -8 n/a 00 cycle time for cl= -10 n/a 00 -12 n/a 00 26 sdram access form clock(3rd highest cas latency) -8 n/a 00 tac for cl= -10 n/a 00 -12 n/a 00 27 precharge to active minimum -8 24ns 18 -10 30ns 1e -12 30ns 1e 28 row active to row active min. -8 16ns 10 -10 20ns 14 -12 24ns 18 4
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 29 ras to cas delay min -8 24ns 18 -10 30ns 1e -12 30ns 1e 30 active to precharge min -8 56ns 38 -10 60ns 3c -12 70ns 46 31 density of each bank on module 128mbyte 20 32-61 superset information (may be used in future) option 00 62 spd revision rev 1 01 63 checksum for bytes 0-62 check sum for -8 51 check sum for -10 c5 check sum for -12 13 64-71 manufactures jedec id code per jep-108e mitsubishi 1cffffffffffffff 72 manufacturing location miyoshi,japan 01 tajima,japan 02 nc,usa 03 germany 04 73-90 manufactures part number mh16s72ama-8 4d483136533732414d412d382d38202020202020 mh16s72ama-10 4d483136533732414d412d313031302020202020 MH16S72AMA-12 4d483136533732414d412d313231322020202020 91-92 revision code pcb revision rrrr 93-94 manufacturing date year/week code yyww 95-98 assembly serial number serial number ssssssss 99-125 manufacture specific data option 00 126 intetl specification frequency 66mhz 66 127 intel specification cas# latency support cl=3: 04h, cl=2/3: 06h 06 128+ unused storage locations open 00 serial presence detect table i i 5
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 pin function input master clock:all other inputs are referenced to the rising edge of ck cke0 input clock enable:cke controls internal clock.when cke is low,internal clock for the following cycle is ceased. cke is also used to select auto / self refresh. after self refresh mode is started, cke e becomes asynchronous input.self refresh is maintained as long as cke is low. /s (/s0,/s2) input chip select: when /s is high,any command means no operation. /ras,/cas,/we input combination of /ras,/cas,/we defines basic commands. a0-11 input a0-11 specify the row/column address in conjunction with ba.the row address is specified by a0-11.the column address is specified by a0-9.a10 is also used to indicate precharge option.when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, both banks are precharged. ba0,1 input bank address:ba0,1 is not simply ba.ba specifies the bank to which a command is applied.ba0,1 must be set with act,pre,read,write commands dq0-63,cb0-7 input/output data in and data out are referenced to the rising edge of ck dqmb0-7 input din mask/output disable:when dqmb is high in burst write.din for the current cycle is masked.when dqmb is high in burst read,dout is disabled at the next but one cycle. vdd,vss power supply power supply for the memory mounted module. scl sda sa0-3 input output input serial clock for serial pd serial data for serial pd address input for serial pd 6 ck (ck0 ~ ck3)
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 basic functions /s chip select : l=select, h=deselect /ras command /cas command /we command cke refresh option @refresh command a10 precharge option @precharge or read/write command ck define basic commands the mh16s72ama provides basic functions,bank(row)activate,burst read / write, bank(row)precharge,and auto / self refresh. each command is defined by control signals of /ras,/cas and /we at ck rising edge. in addition to 3 signals,/s,cke and a10 are used as chip select,refresh option,and precharge option,respectively. to know the detailed definition of commands please see the command truth table. activate(act) [/ras =l, /cas = /we =h] read(read) [/ras =h,/cas =l, /we =h] write(write) [/ras =h, /cas = /we =l] precharge(pre) [/ras =l, /cas =h,/we =l] auto-refresh(refa) [/ras =/cas =l, /we =cke =h] act command activates a row in an idle bank indicated by ba. read command starts burst read from the active bank indicated by ba.first output data appears after /cas latency. when a10 =h at this command,the bank is deactivated after the burst read(auto-precharge, reada ). write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write(auto-precharge, writea ). pre command deactivates the active bank indicated by ba. this command also terminates burst read / write operation. when a10 =h at this command, both banks are deactivated(precharge all, prea ). pefa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically. 7
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 command truth table command mnemonic ck n-1 ck n /s /ras /cas /we ba a10 a0-9 ,a11 deselect desel h x h x x x x x x no operation nop h x l h h h x x x row adress entry & bank activate act h x l l h h v v v single bank precharge pre h x l l h l v l x precharge all bank prea h x l l h l v h x column address entry & write write h x l lh h l v l v column address entry & write with auto- precharge writea h x l h l l v h v column address entry & read read h x l h l h v l v column address entry & read with auto precharge reada h x l h l h v h v auto-refresh refa h h l hl l h x x x self-refresh entry refs h l l l l h x x x self-refresh exit refsx l h h lx x x x x x l h l h h h x x x burst terminate term h x l h h l x x x mode register set mrs h x l l l l l l v*1 h =high level, l = low level, v = valid, x = don't care, n = ck cycle number note: 1.a7-9 = 0, a0-6 = mode address 8
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 current state /s /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act bank active,latch ra l l h l ba,a10 pre/prea nop*4 l l l h x refa auto-refresh*5 l l l l op-code, mode-add mrs mode register set*5 row active h x x x x desel nop l h h h x nop nop l h h l ba tbst nop l h l h ba,ca,a10 read/reada begin read,latch ca, determine auto-precharge l h l l ba,ca,a10 write/ writea begin write,latch ca, determine auto-precharge l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea precharge/precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal read h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l ba tbst terminate burst l h l h ba,ca,a10 read/reada terminate burst,latch ca, begin new read,determine auto-precharge*3 l h l l ba,ca,a10 write/writea terminate burst,latch ca, begin write,determine auto- precharge*3 l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea terminate burst,precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal function truth table 9
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 function truth table (continued) current state /s /ras /cas /we address command action write h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l ba tbst terminate burst l h l h ba,ca,a10 read/reada terminate burst,latch ca, begin read,determine auto- precharge*3 l h l l ba,ca,a10 write/ writea terminate burst,latch ca, begin write,determine auto- precharge*3 l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea terminate burst,precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal read with h x x x x desel nop(continue burst to end) auto l h h h x nop nop(continue burst to end) precharge l h h l ba tbst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 write/ writea illegal l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write with h x x x x desel nop(continue burst to end) auto l h h h x nop nop(continue burst to end) precharge l h h l ba tbst illegal l h l h ba,ca,a10 read/reada illegal l h l l ba,ca,a10 write/ writea illegal l l h h ba,ra act bank active/illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal 10
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 function truth table (continued) current state /s /ras /cas /we address command action pre - h x x x x desel nop(idle after trp) charging l h h h x nop nop(idle after trp) l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act illegal*2 l l h l ba,a10 pre/prea nop*4(idle after trp) l l l h x refa illegal l l l l op-code, mode-add mrs illegal row h x x x x desel nop(row active after trcd activating l h h h x nop nop(row active after trcd l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal write re- h x x x x desel nop covering l h h h x nop nop l h h l ba tbst illegal*2 l h l x ba,ca,a10 read/write illegal*2 l l h h ba,ra act illegal*2 l l h l ba,a10 pre/prea illegal*2 l l l h x refa illegal l l l l op-code, mode-add mrs illegal 11
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 function truth table (continued) current state /s /ras /cas /we address command action re- h x x x x desel nop(idle after trc) freshing l h h h x nop nop(idle after trc) l h h l ba tbst illegal l h l x ba,ca,a10 read/write illegal l l h h ba,ra act illegal l l h l ba,a10 pre/prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal mode h x x x x desel nop(idle after trsc) register l h h h x nop nop(idle after trsc) setting l h h l ba tbst illegal l h l x ba,ca,a10 read/write illegal l l h h ba,ra act illegal l l h l ba,a10 pre/prea illegal l l l h x refa illegal l l l l op-code, mode-add mrs illegal abbreviations: h = hige level, l = low level, x = don't care ba = bank address, ra = row address, ca = column address, nop = no operation notes: 1. all entries assume that cke was high during the preceding clock cycle and the current clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by ba, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, write recovery requirements. 4. nop to bank precharging or in idle state.may precharge bank indicated by ba. 5. illegal if any bank is not idle. illegal = device operation and / or date-integrity are not guaranteed. 12
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 function truth table for cke current state ck n-1 ck n /s /ras /cas /we add action self - h x x x x x x invalid refresh*1 l h h x x x x exit self-refresh(idle after trc) l h l h h h x exit self-refresh(idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal l l x x x x x nop(maintain self-refresh) power h x x x x x x invalid down l h x x x x x exit power down to idle l l x x x x x nop(maintain self-refresh) all banks h h x x x x x refer to function truth table idle*2 h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal l x x x x x x refer to current state = power down any state h h x x x x x refer to function truth table other than h l x x x x x begin ck0 suspend at next cycle*3 listed above l h x x x x x exit ck0 suspend at next cycle*3 l l x x x x x maintain ck0 suspend abbreviations: h = high level, l = low level, x = don't care notes: 1. cke low to high transition will re-enable ck and other inputs asynchronously . a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only form the all banks idle state. 3. must be legal command. 13
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 simplified state diagram row active idle pre charge auto refresh self refresh mode register set power down read reada write writea read suspend reada suspend write suspend writea suspend power on clk suspend ckel ckeh ckel ckeh ckel ckeh ckel ckeh act refa refs refsx ckel ckeh mrs ckel ckeh write read writea writea reada write read pre reada writea reada pre pre pre power applied automatic sequence command sequence 14
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqmb0-7 high and nop condition at the inputs. 2. maintain stable power, stable cock, and nop input conditions for a minimum of 500?. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation. mode register r:reserved for future use /s /ras /cas /we ba0,1 a11-0 ck v burst length, burst type and /cas latency can be programmed by setting the mode register(mrs). the mode register stores these date until the next mrs command, which may be issue when both banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. 15 bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 burst length bt= 0 bt= 1 1 2 4 8 r r r r 1 2 4 8 r r r r 0 1 burst type sequential interleaved a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba0 0 0 0 0 0 ltmode bt bl 0 0 cl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 latency mode /cas latency 2 3 r r r r r r
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 command address ck read y q0 q1 q2 q3 write y d0 d1 d2 d3 /cas latency burst length burst length dq burst type cl= 3 bl= 4 a2 a1 a0 initial address bl sequential interleaved column addressing 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 - 0 0 - 0 1 - 1 0 - 1 1 - - 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 7 0 1 2 0 1 2 3 1 2 3 0 2 3 0 1 3 0 0 1 7 6 5 4 0 1 2 3 1 0 3 2 2 3 0 1 3 2 0 1 - - 1 1 2 1 0 3 4 5 6 3 2 1 0 1 0 1 0 8 4 2 16
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 bank activation and precharge all (bl=4, cl=3) ck command a0-9,11 a10 ba0,1 dq act xa xa 00 read y 0 00 qa0 qa1 qa2 qa3 act xb xb 01 pre trrd trcd 1 act xb xb 01 precharge all tras trp operation description bank activate the sdram has two independent banks. each bank is activated by the act command with the bank address(ba0,1). a row is indicated by the row address a11-0. the minimum activation interval between one bank and the other bank is trrd. precharge the pre command deactivates indicated by ba. when both banks are active, the precharge all command(prea,pre + a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command can be issued. read after trcd from the bank activation, a read command can be issued. 1st output date is available after the /cas latency from the read, followed by (bl-1) consecutive date when the burst length is bl. the start address is specified by a9-0, and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time(trp) can be hidden behind continuous output data(in case of bl=8) by interleaving the dual banks. when a10 is high at a read command, the auto-precharge(reada) is performed. any command (read, write, pre, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge start timing depends on /cad latency. the next act command can be issued after trp from the internal precharge timing. 17
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 dual bank interleaving read (bl=4, cl=3) ck command a0-9,11 a10 ba0,1 dq act xa xa 0 read y 0 0 read y 0 1 qa0 qa1 qa2 qa3 qb0 qb1 qb2 act xb xb 1 pre 0 0 trcd /cas latency burst length read with auto-precharge (bl=4, cl=3) ck command a10 dq act xa xa 0 read y 1 0 qa0 qa1 qa2 qa3 act xa xa 0 internal precharge begins trcd trp read auto-precharge timing (bl=4) ck command act read internal precharge start timing dq qa0 qa1 qa2 qa3 dq qa0 qa1 qa2 qa3 cl=3 cl=2 18 a0-9,11 ba0,1
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 dual bank interleaving write (bl=4) ck command a10 dq act xa xa 0 write y 0 0 write y 0 1 da0 da1 da2 da3 act xb xb 1 pre 0 0 trcd burst length db0 db1 db2 db3 trcd twr ck command a10 dq act xa xa 0 write y 1 0 da0 da1 da2 da3 act xa xa 0 internal precharge begins trcd trp twr write with auto-precharge (bl=4) write after trcd from the bank activation, a write command can be issued. 1st input data is set at the same cycle as the write. following(bl-1) data are written into the ram, when the burst length is bl. the start address is specified by a9-0, and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time(trp) can be hidden behind continuous input data (in case of bl=8) by interleaving the dual banks. from the last input data to the pre command, the write recovery time (twr) is required. when a10 is high at a write command, the auto-precharge(writea) is performed. any command(read, write, pre, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge begins at twr after the last input data cycle. the next act command can be issued after trp from the internal precharge timing. 19 a0-9,11 ba0,1 a0-9,11 ba0,1
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 burst interruption [ read interrupted by read ] burst read option can be interrupted by new read of the same or the other bank. mh16s72ama allows random column access. read to read interval is minimum 1 ck read interrupted by read (bl=4, cl=3) ck command a10 dq read yi 0 0 read yk 0 1 qai0 qaj1 qbk0 qbk1 read yj 0 0 qaj0 qbk2 qal0 read yl 0 0 qal1 qal2 qal3 [ read interrupted by write ] burst read operation can be interrupted by write of the same or the other bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqmb0-7 to prevent the bus contention. the output is disabled automatically 2 cycle after write assertion. read interrupted by write (bl=4, cl=3) ck command a10 q read yi 0 0 qai0 write yj 0 0 d daj0 daj1 daj2 daj3 dqmb0-7 dqm control write control 20 a0-9,11 ba0,1 a0-9,11 ba0,1
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 [ read interrupted by precharge ] burst read operation can be interrupted by precharge of the same or the other bank. read to pre interval is minimum 1 ck. a pre command disables the data output, depending on the /cas latency. the figure below shows examples, when the dataout is terminated. read interrupted by precharge (bl=4) ck command dq read pre q0 q1 command dq read pre q0 q1 command dq read pre q0 q2 q3 q1 command dq read pre q0 q1 q2 q3 cl=3 cl=2 comman d dq rea d pre q 0 q 2 q 3 q 1 comman d dq rea d pr e q 0 q 1 cl= 1 21
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 [ read interrupted by burst terminate ] similarly to the precharge, burst terminate command can interrupt burst read operation and disable the data output. read to term interval is minimum 1 ck. the figure below shows examples, when the dataout is terminated. read interrupted by burst terminate (bl=4) ck command dq read term q0 q1 q2 q3 cl=3 command dq read term q0 q1 q2 command dq read term q0 command dq read term q0 q1 q2 q3 cl=2 command dq read term q0 q1 q2 command dq read term q0 comman d dq rea d term q 0 q 1 q 2 q 3 cl= 1 comman d dq rea d term q 0 22
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 [ write interrupted by write ] burst write operation can be interrupted by new write of the same or the other bank. random column access is allowed. write to write interval is minimum 1 ck. write interrupted by write (bl=4) ck command a10 dq write yi 0 0 write yk 0 1 dai0 daj0 daj1 dbk0 write yj 0 0 dbk1 dbk2 write yl 0 0 dal0 dal1 dal2 dal3 [ write interrupted by read ] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. write to read interval is minimum 1 ck. the input data on dq at the interrupting read cycle is "don't care". write interrupted by read (bl=4, cl=3) ck command a10 dq write yi 0 0 qaj0 read yj 0 0 qaj1 dai0 dak0 dak1 dqmb0-7 write yk 0 0 read yl 0 1 qbl0 23 a0-9,11 ba0,1 a0-9,11 ba0,1
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 [ write interrupted by precharge ] burst write operation can be interrupted by precharge of the same bank. random column access is allowed. because the write recovery time(twr) is required between the last input data and the next pre, 3rd data should be masked with dqmb0-7 shown as below. write interrupted by precharge (bl=4) ck command a10 dq write yi 0 0 pre 0 0 dai0 dai1 dqmb0-7 act xb xb 0 twr trp this data should be masked to satisfy twr requirement. [ write interrupted by burst terminate ] burst terminate command can terminate burst write operation. in this case, the write recovery time is not required and the bank remains active. the figure below shows the case 3 words of data are written. random column access is allowed. write to term interval is minimum 1 ck. write interrupted by burst terminate (bl=4) ck command a10 dq write yi 0 0 term dai0 dai1 dqmb0-7 dai2 24 a0-9,11 ba0,1 a0-9,11 ba0,1
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 auto refresh single cycle of auto-refresh is initiated with a refa(/cs=/ras=/cas=l, /we=/cke=h) command. the refresh address is generated internally. 4096 refa cycle within 64ms refresh 64mbit memory cells. the auto-refresh is performed on 4bank alternately(ping-pong refresh). before performing an auto-refresh, both banks must be in the idle state. additional commands must not be supplied to the device before trc from the refa command. auto-refresh ck /s /ras /cas /we cke a0-11 ba0,1 auto refresh on bank 0 auto refresh on bank 1 minimum trc nop or deslect 25
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 self refresh self-refresh mode is entered by issuing a refs command (/cs=/ras=/cas=l, /we=h, cke=l). once the self-refresh is initiated, it is maintained as log as cke is kept low.during the self-refresh mode, cke is asynchronous and the only enabled input (but asynchronous), all other inputs including ck0 are disabled and ignored, and power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable ck0 inputs, asserting desel or nop command and then asserting cke(refsx). after trc from refsx both banks are in the idle state and a new command can be issued after trc, but desel or nop commands must be asserted till then. self-refresh ck /s /ras /cas /we cke a0-11 ba0,1 self refresh entry self refresh exit x 0 minimum trc for recovery stable ck nop new command 26
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 clk suspend cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous input except during the self-refresh mode. clk suspend can be performed either when the banks are active or idle, but a command at the following cycle is ignored. ck (ext.clk) cke int.clk power down by cke ck command pre cke command cke act nop nop nop nop nop nop nop nop nop nop nop nop standby power down active power down nop nop dq suspend by cke ck command dq write d0 d1 d2 d3 cke read q0 q1 q2 q3 27
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 dqm control dqmb0-7 is a dual function signal defined as the data mask for writes and the output disable for reads. during writes, dqmb0-7 masks input data word by word. dqmb0-7 to write mask latency is 0. during reads, dqmb0-7 forces output to hi-z word by word. dqmb0-7 to output hi-z latency is 2. dqm function ck command dq write d0 d2 d3 dqmb0-7 read q0 q1 q3 masked by dqm=h disabled by dqm=h 28
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 absolute maximum ratings symbol parameter condition ratings unit vdd vi vo io pd topr tstg supply voltage input voltage output voltage output current power dissipation operating temperature storage temperature with respect to vss with respect to vss with respect to vss ta=25? -0.5 ~ 4.6 -0.5 ~ vdd+0.5 50 18 0 ~ 70 -40 ~ 100 v v v ma w ? ? recommended operating condition (ta=0 ~ 70?, unless otherwise noted) symbol vdd vss vih vil parameter supply voltage high-level input voltage all inputs supply voltage low-level input voltage all inputs limits unit min. typ. max. 3.0 0 2.0 -0.3 3.3 0 3.6 0 vdd+0.3 0.8 v v v v capacitance (ta=0 ~ 70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) symbol ci(a) ci(c) ci(k) ci/o parameter input capacitance, address pin input capacitance, control pin input capacitance, ck pin input capacitance, i/o pin test condition limits(max.) unit vi = vss f=1mhz vi=25mvrms 105 105 40 22 pf pf pf pf 29 -0.5 ~ vdd+0.5
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 average supply current from vdd (ta=0 ~70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) ac operating conditions and characteristics (ta=0 ~ 70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) symbol parameter test condition limits unit min. max. voh(dc) high-level output voltage(dc) ioh=-2ma 2.4 v vol(dc) low-level output voltage(dc) iol=2ma 0.4 v voh(ac ) high-level output voltage(ac) cl=50pf, ioh=-2ma 2 v vol(ac) low-level output voltage(ac) cl=50pf, iol=2ma 0.8 v ioz off-stare output current q floating vo=0 ?` vdd -1 0 1 0 ? a ii input current vih=0 ?` vdd+0.3v -8 0 8 0 ? a symbol parameter test condition limits(max) unit -8 -10 -12 icc1s operating current, single bank trc=min.tclk=min, bl=1, cl=3 1710 1530 1350 ma icc1d operating current, dual bank trc=min.tclk=min, bl=1, cl=3 2340 2070 1890 icc2h standby current, cke=h both banks idle, tclk=min, cke=h 450 396 360 ma icc2l standby current, cke=l both banks idle, tclk=min, cke=l 36 36 36 ma icc3 active standby current 900 810 720 ma icc4 burst current tclk=min, bl=4, cl=3, both banks active(discerte) 2340 2070 1890 ma icc5 auto-refresh current trc=min, tclk=min 2340 2070 1890 ma icc6 self-refresh current cke <0.2v 18 18 18 ma both banks active, tclk=min, cke=h ma 30 ioz off-stare output current q floating vo=0 ~ vdd -10 10 ua ii input current vih=0 ~ vdd+0.3v -180 180 ua (discrete) (discrete)
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 max. ac timing requirements (sdram component) (ta=0 ~ 70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) input pulse levels: 0.8v to 2.0v input timing measurement level: 1.4v limits symbol parameter -10 -12 unit min. max. min. max. tclk ck cycle time 15 15 ns 12 ns tch ck high pulse width 4 10 4 ns tcl ck low pilse width 4 4 ns tt transition time of ck 1 10 1 10 ns tis input setup time(all inputs) 3 3 ns tih input hold time(all inputs) 1 ns trc row cycle time 90 100 ns trcd row to column delay 30 30 ns tras row active time 60 10000 70 10000 ns trp row precharge time 30 30 ns twr write recovery time 10 12 ns trrd act to act deley time 20 24 ns trsc mode register set cycle time 20 24 ns tpde power down exit time 10 12 ns tref refresh interval time 64 64 ms ck signal 1.4v 1.4v any ac timing is referenced to the input signal crossing through 1.4v. 31 cl=2 cl=3 min. -8 12 3 8 3 1 10 2 1 80 24 56 10000 24 10 16 16 8 64 1
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 1.4v 1.4v dq ck tac toh tohz switching characteristics (sdram component) (ta=0 ~ 70?, vdd = 3.3 ?0.3v, vss = 0v, unless otherwise noted) limits symbol parameter -8 -10 -12 unit min. max. min. max. min. max. tac access time from ck cl=2 8 9 9.5 ns cl=3 8 8 8 ns toh output hold time 2.5 3 3 ns from ck tolz delay time, output low impedance from ck 0 0 0 ns tohz delay time, output high impedance from ck 2.5 7 3 8 3 ns output load condition v out 50pf 50 w v tt =1.4v dq ck output timing measurement reference point 1.4v 1.4v 32 8
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 burst write (single bank) @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 pre#0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd twr trp trc trcd clk italic parameter indicates minimum case tras a0-9 a10 dqm a11 33
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 burst write (multi bank) @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 1 d0 d0 d0 d0 x x 0 y 0 d0 d0 d0 d0 act#0 write#0 pre#0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras twr trp trc trcd d1 d1 d1 d1 x x x 1 trrd y twr 0 x 1 x x x 2 trrd act#1 write#1 pre#1 act#2 clk italic parameter indicates minimum case a0-9 a10 dqm a11 34
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 burst read (single bank) @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 x x x 0 y 0 q0 q0 act#0 read#0 pre#0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras trp trc trcd cl=3 read to pre 3 bl allows full data out dqm read latency =2 clk italic parameter indicates minimum case a0-9 a10 dqm a11 35
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 burst read (multiple bank) @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 x x x 0 y 0 q0 act#0 read#0 pre#0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd tras trp trc trcd cl=3 dqm read latency =2 trrd x x x 1 act#1 y 1 trrd q1 q1 q1 q1 x x x 2 1 cl=3 read#1 pre#1 act#2 clk italic parameter indicates minimum case a0-9 a10 dqm a11 36
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 burst write (multi bank) with auto-precharge @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 1 d0 d0 d0 d0 x x 0 y 0 d0 d0 d0 d0 act#0 write#0 with autoprecharge act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd trc trcd d1 d1 d1 d1 x x x 1 trrd y x 1 x x x trrd act#1 write#1 with autoprecharge bl-1+ twr + trp y 1 d1 trcd act#1 write#1 clk bl-1+ twr + trp italic parameter indicates minimum case a0-9 a10 dqm a11 37
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 burst read (multiple bank) with auto-precharge @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 q0 q0 q0 q0 x x x 0 y 0 q0 act#0 read#0 with auto-precharge act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd trc trcd cl=3 dqm read latency =2 trrd x x x 1 act#1 y 1 trrd q1 q1 q1 q1 cl=3 read#1 with auto-precharge act#1 bl+ trp bl+ trp x x x 1 y 1 clk q0 cl=3 trcd italic parameter indicates minimum case a0-9 a10 dqm a11 38
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 page mode burst write (multi bank) @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 act#0 write#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd d1 d1 d1 d1 y y 0 write#1 clk x x x 1 trrd 1 y d0 d0 d0 d0 d0 d0 d0 act#1 write#0 italic parameter indicates minimum case a0-9 a10 dqm a11 39
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 page mode burst read (multi bank) @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 act#0 read#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q1 q1 q1 q1 y y 0 read#1 clk x x x 1 trrd 1 y q0 q0 q0 q0 act#1 read#0 q0 cl=3 cl=3 cl=3 dqm read latency=2 italic parameter indicates minimum case a0-9 a10 dqm a11 40
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 write interrupted by write / read @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q0 write#1 clk x x x 1 trrd 1 y d0 d0 d1 d1 q0 q0 q0 act#1 write#0 y y 0 0 0 y tccd cl=3 write#0 read#0 burst write can be interrupted by write or read of any active bank. italic parameter indicates minimum case a0-9 a10 dqm a11 41
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 read interrupted by read / write @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 act#0 read#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd q0 d0 d0 y y 0 read#1 clk x x x 1 trrd 0 y q0 q0 q1 q1 act#1 read#0 q0 dqm read latency=2 0 y 1 y burst read can be interrupted by read or write of any active bank. read#0 read#0 blank to prevent bus contention italic parameter indicates minimum case a0-9 a10 dqm a11 42
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 write interrupted by precharge @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 d0 d0 d0 d0 act#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd write#1 clk x x x 1 trrd 1 d1 d1 d1 d1 d1 act#1 y 1 1 y burst write is not interrupted by precharge of the other bank. 0 x x x 1 pre#1 pre#0 act#1 write#1 burst write is interrupted by precharge of the same bank. italic parameter indicates minimum case a0-9 a10 dqm a11 43
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 read interrupted by precharge @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 q0 q0 q0 act#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd y 1 pre#1 clk x x x 1 trrd q1 q1 act#1 pre#0 q0 dqm read latency=2 1 y 1 burst read is not interrupted by precharge of the other bank. 0 x x x 1 trcd trp read#1 act#1 read#1 burst read is interrupted by precharge of the same bank. italic parameter indicates minimum case a0-9 a10 dqm a11 44
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 mode register setting /cs /ras /cas /we cke ba0,1 dq auto-ref (last of 8 cycles) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 y 0 clk trc d0 mode register setting m 0 x x x 0 trcd trsc act#0 write#0 d0 d0 d0 italic parameter indicates minimum case a0-9 a10 dqm a11 45
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 auto-refresh @bl=4 /cs /ras /cas /we cke ba0,1 dq auto-refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 clk trc before auto-refresh, all banks must be idle state. y 0 d0 x x x 0 trcd act#0 write#0 d0 d0 d0 after trc from auto-refresh, all banks are idle state. italic parameter indicates minimum case a0-9 a10 dqm a11 46
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 self-refresh /cs /ras /cas /we cke ba0,1 dq self-refresh entry 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 clk before self-refresh entry, all banks must be idle state. x x x 0 self-refresh exit act#0 after trc from self-refresh exit, all banks are idle state. trc tsrx clk can be stopped cke must be low to maintain self-refresh italic parameter indicates minimum case a0-9 a10 dqm a11 47
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 dqm write mask @bl=4 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 d0 d0 d0 d0 y 0 d0 d0 d0 act#0 write#0 write#0 write#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y masked masked italic parameter indicates minimum case a0-9 a10 dqm a11 48
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 dqm read mask @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 y 0 q0 q0 q0 act#0 read#0 read#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y masked masked dqm read latency=2 italic parameter indicates minimum case a0-9 a10 dqm a11 49
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 power down /cs /ras /cas /we cke ba0,1 dq 0 precharge all act#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 clk x x x standby power down active power down cke latency=1 italic parameter indicates minimum case a0-9 a10 dqm a11 50
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 clk suspend @bl=4 cl=3 /cs /ras /cas /we cke ba0,1 dq x x x 0 y 0 0 q0 q0 q0 q0 act#0 write#0 read#0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 trcd clk y d0 d0 d0 d0 clk suspended clk suspended cke latency=1 cke latency=1 italic parameter indicates minimum case a0-9 a10 dqm a11 51
mh16s72ama -8,-10,-12 1207959552-bit (16777216 - word by 72-bit)synchronousdram mitsubishi lsis ( / 52 ) mitsubishi electric 5. mar.1997 preliminary spec. some contents are subject to change without notice. mit-ds-0128-0.0 52 1.27 ?.1 133.35 ?.13 3.9max 31.75 ?.13 84 1 127.35 ?.13 17.78 ?.13 3 ?.13 1 ?.13 3 ?.13 2 ?.13 6.35 ?.13 24.495 0.13 8.89 ?.13 29x1.27=36.83 ?.2 42.18 0.13 9x1.27=11.43 ?.2 6.35 ?.1 43x1.27=54.61 ?.2 1.27 ?.1 2-? ?.1 17.78 ?.13 2-r2 ?.13 1 ?.13 168 85 outline preliminary

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